Company Products Tech.Info Notice    Dev.Tools Home > Developement Guide > FAQ FAQ HMS30C7202  :  ADCLCDPMU PLL RESETSDRAM SMI MMCUART CAN SPI USBTIMER PWM PS2 KEDGPIOAPPLICATION HMS30C7201  :  ADCPMU PLLETCAPPLICATION Q1. I use an external RTC device with a backup battery. This voltage of the backup battery is measured by the 7202 ADC (ADIN[3]). At power down (the RTC is powered by the battery) the 7202 ADIN[3] draws 0,5mA (the RTC needs only 1.6uA). Can you suggest a solution? A1. If you turned off the VDD power of 7202, transmission gate of ADC would not be in normal bias condition. All bias for gate and drain, source terminal and well would be in un-known state, just substrate of CMOS transistor connected to GND. In this case, ADC input current could be leaked from source terminal through well and substrate(or drain terminal too) of CMOS transmission gate. So if user wanted to tuned off VDD of 7202, backup battery sensing line should be separated from ADC input pin when power off. Q2. The ADC clock frequency aclk is 2..8MHz (ch.12.3). Is this an internal RC oscillator or why is the range so large? A2. The ADC of 7202 uses 3.6864 MHz for ADC operation.This clock comes from Oscillator input clock but re-synced with BCLK.If you mentioned about ADC characteristics, that information just shows ADC IP characteristics of 7202. Q3. The conversion time is aclk/16. Because aclk has such a large range,how do I know exactly when the conversion is done? I cannot find a dedicated "conversion ready" bit or interrupt in direct access mode. A3. "aclk" is 3.6864MHz.This ADC keeps converting at every 16 aclk with input level when AIOSTOP is low.But there's no way to check the exact time of one AD conversion cycle complete. Because we made a direct control register for ADC malfunction cases.(We just read continuously from Direct Data register to test ADC with S/W) Q4. Register ADCCR, WAIT bits (ch.10.2.1.2) : what is the "ADC conversion wait time"? Is this sampling time (charge internal S&H capacitor) before actual conversion starts? A4. No, it is for capture timing of the data from ADC to internal register.If ADC conversion complete time was just same with data capture time.User could get un-stable value of AD conversion. (At after every 16 aclk cycle, AD conversion finish and logic read AD value at the same time from ADC IP. If reading data is not stable, user will have four wrong data.) So we made this register to get minimum 3 stable value of AD conversion. Q5. Is there no problem with corrupt/unstable data samples in automatic mode? A5. Yes, user may get a corrupt data, so touch panel and battery check function give 4 data for one sample point.In 7202 user can not control timing of ADC exactly, MagnaChip recommend having more samples(also for direct access mode) to get rid of exceptional value (It may be corrupt value or cause from noise) from some range of the average. Q6. WAIT bits(ch.10.1.2.1): "11: read ADC data on negative edge of ADEND signal".What is the ADEND signal? It is nowhere else in the datasheet. A6. ADEND means "conversion ready". Internal logic designed to read ADC data at every 16 or 18 or 20 aclk and at negative edge of ADEND signal.But it was found sometimes it did not work properly with ADEND and missed some logic to use this signal for good reason.(We'll update datasheet in the near future. it may remove in next version) Q7. If I set ADCCR.SOP=0, does the ADC convert all the time at maximum rate?If so: what is this rate, and how do I know when there is a new sample in ADCDIRDATA? A7. In direct control mode, SOP bit would not affect the operation of ADC.It's hard to read AD data from Direct Data register with a fixed period. Q8. Bit ADCSDCR.SRATE: does this bit have any effect on sampling rate in direct access mode (other than on calibration time)? A8. This bit would not affect the operation of direct control mode. Q9. Sampling rate 8/11kHz: from which clock is this derived? FCLK/CCLK/aclk? A9. aclk, it means 3.6864 MHz (in Slow APB, it's called as "PCLK"). Q10. I assume there is a S&H capacitor at the ADC input. What is the equivalent input circuit (usually this is given in terms of series resistance and capacitance to GND)? How long is the sampling time? I need to know this because I have relatively large source impedance ( > 30kOhms), and must calculate the capacitor needed to buffer the input. A10. Yes, there's sample and hold circuit for AD input.The input impedance would be above 1-3 Mega Ohm. Q11. If I use the sound data capture unit (automatic sample, not direct access): when is the interrupt generated: after 1 sample, after 4 samples (one ADCSDATA register), or after 32 samples (all ADCSDATA registers)? The latter makes sense, because it has the lowest interrupt rate and one can read all 8 ADCSDATA registers at once. A11. Yes the latter is correct, interrupt will generate when each data register is full. (for the sound, all the 8 registers are filled then make interrupt) Q12. When the interrupt occurs, how much time do I have to read ADCSDATA0..7 before ADCSDATA0 is overwritten with the next sound sample? Is it 125us (1 / 8kHz), or is it after 4x125us (when all 4 8bit samples for ADCSDATA0 are complete)? A12. In ADC interface logic, there are 8-Byte(2-word) temporal buffer for sound data and every 2 words write into SDATA0,1 / SDATA2,3 / SDATA4,5 / SDATA6,7 at a time (at end of every "all 8-Byte temporal buffer full" time) So, user has to read in 8x (one sampling period) seconds for getting valid ADCSDATA0, 1 (1st 2-word) after Sound interrupt. Q13. Is the following correct/possible to do: 1. INIT: Set ADCCR.ADCPD=0, .DIRECTC=1, .SOP=1 for power on, direct access,one-shot operation;     then wait calibration time 2. Select ADC channel with ADCDIRCR.ACH and set ADCDIRCR.AIOSTOP=0 to Start conversion     (one register write access).     (When conversion is over, the ADC sets AIOSTOP=1 and data is available in ADCDIRDATA) 3. After some time (e.g. 0.5ms -> sampling rate 2kHz): read value from ADCDIRDATA 4. Repeat with 2. A13. from step 2 to step 3 If once AIOSTOP went high, it would take about 20-40 ms to complete self-calibration for next time AIOSTOP low.So if ADC wanted to read continuously, AIOSTOP should stay at low.And AIOSTOP would not go "high" if user did not write "1" on bit position of AIOSTOP at direct control mode. Q14. What in the input impedance for the ADIN[0..4]? A14. Input impedance of ADIN[0..4] is more than a couple of Mega Ohms.Because input signal goes to "gate" terminal of CMOS Transistor. Q15. What is the input impedance or current consumption of AVREFADC? A15. Equivalent circuit of AVREFADC is about 5 KOhm of resistance to GND. Q16. Can we adjust the input range by setting AVREFADC to a voltage different from AVDDADC (e.g. AVREFADC = 2.048V, AVDDADC = 3.3V)? A16. Yes, you can. But in low AVREFADC voltage, SNR might be worse than the specifications. Q17. I assume there is a S&H capacitor at the ADC input. What is the equivalent input circuit (usually this is given in terms of series resistance and capacitance to GND)? How long is the sampling time? I need to know this because I have relatively large source impedance ( > 30kOhms), and must calculate the capacitor needed to buffer the input. A17. S&H capacitor is consisted about 500Ohm resistor and 300 fF capacitor as a series. The sampling time is 1clock.